# IBM staff say a model tuned on its own VHDL is deployed for its logic designers to explain existing hardware design code

Page: https://flyvolo.ai/en/changes/ev-20250514-chip-design-engineer-14
Date: 2025-05-14 · Stage: Deployment
Can this record move a task judgement? yes
Occupation: https://flyvolo.ai/en/careers/chip-design-engineer

## Scope

United States, one employer. A paper by the employer's staff says an instruction-tuned model customised on its VHDL has been deployed for use by logic designers, who paste code and get an explanation; that the thumbs-up to thumbs-down ratio is running at about 70% to 30%; and that the company is deploying it to help new designers get up to speed on existing designs. The first implementation is feedback-oriented; the model explains code rather than writing it, and no change in designers' time is measured.

## Source

- Dupuis, Nair, Ramji et al. (IBM Research and IBM Infrastructure) — 'Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors', arXiv:2505.09610 (14 May 2025) — https://arxiv.org/abs/2505.09610 (primary source)

## What this means

At one chip maker, reading and understanding existing RTL is now done with a model built on the company's own code.

## What it does not show yet

One employer's own preprint; the tool explains code and does not write it, and no time or staffing effect is given.

## How to verify it yourself

Open arXiv:2505.09610 and find "We have deployed the instruction-tuned model for use by logic designers".


More: https://flyvolo.ai/llms.txt