# Samsung says it automates transistor sizing in its own analog design with reinforcement learning and genetic algorithms, roughly halving design turnaround for HBM4

Page: https://flyvolo.ai/en/changes/ev-20260317-chip-design-engineer-13
Date: 2026-03-17 · Stage: Deployment
Can this record move a task judgement? yes
Occupation: https://flyvolo.ai/en/careers/chip-design-engineer

## Scope

South Korea. The chipmaker's own page on a talk by the head of its device-solutions AI centre says Samsung is applying agentic AI across its design workflows with a focus on analog and logic design, has incorporated reinforcement learning and genetic algorithms to automate transistor sizing, predicts design-rule violations in advance and builds them into layout, and that design turnaround time was reduced by about 50%, enabling up to 13 Gbps per pin in HBM4. The company's own claim about its own chips; who sets the topology and specification is not stated, and the multi-agent layout workflow on the same page is a future plan.

## Source

- Samsung Semiconductor tech blog — 'Samsung Showcases Agentic AI–Driven Semiconductor Engineering Innovation at NVIDIA GTC 2026' (published September 4, 2026; talk of March 17, 2026) — https://semiconductor.samsung.com/news-events/tech-blog/samsung-showcases-agentic-ai-driven-semiconductor-engineering-innovation-at-nvidia-gtc-2026/ (primary source)

## What this means

In a large chipmaker's own analog design, sizing transistors has moved to automated search.

## What it does not show yet

The company's own claim, with nothing on who sets topology and specification.

## How to verify it yourself

Open Samsung Semiconductor's tech blog post on agentic AI at NVIDIA GTC 2026 and find "to automate transistor sizing".


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