Chip design engineer — tasks, one by one

Architecture and specification

No record shows AI setting chip architecture. The benchmarks start from a specification someone else wrote, and the vendor tools optimise against targets engineers set. The US statistics bureau projects computer hardware engineer employment to grow 9 percent from 2025 to 2035, much faster than average, because these workers are needed to design parts for products that use processors, and it does not mention AI.

The absence of a record is not evidence that AI cannot help here, and the projection covers all computer hardware engineers in one country, not chip architects.

Writing RTL

Models write short hardware code but not yet whole designs. On 156 textbook-style problems GPT-4 passed 43.5% on the first try; on 30 larger designs it produced 15 that worked in at least one of five attempts; and on a newer benchmark of problems written by experienced hardware engineers, the best models passed no more than 34% of code-generation problems on the first try. The authors of the first benchmark say it is confined to boilerplate code for relatively small designs.

Benchmarks with models of their time; they check whether code works, not whether it meets power, performance and area, and they do not measure engineers' work.

Verification and debug

Verification is where AI agents struggle most. The benchmark written by experienced hardware engineers found agentic tasks involving verification and reuse of existing designs particularly difficult. NVIDIA's paper on its internal chip-design models says its own internal studies found up to 60% of a typical chip designer's time goes to debug or checklist tasks, and its models were competitive at summarising bugs — a help to the engineer, not a replacement for the checking.

A benchmark and a company's account of its internal models; the 60% figure comes from internal studies the paper does not publish.

Floorplanning, placement and timing closure

Optimisation tools are in production use, and the claims about how far they go are contested. Google's 2021 paper said its reinforcement-learning method produced floorplans superior or comparable to humans in under six hours; an independent review at the University of California, San Diego found human experts beat it on 5 of 6 comparisons for large macro-heavy designs, while it beat a stronger conventional algorithm on one timing measure. Synopsys says customers have taped out more than 100 commercial chips with its AI design-space optimisation tool. Engineers still set the constraints and close the design.

The adoption figure comes from a tool vendor about its own product and the layout method is its developer's; the independent review tests a handful of designs, and none measures engineers' time.

Analog and custom circuit design

Analog design has long depended on expert intuition, and research tools are starting to take on the search. An academic system trained with reinforcement learning met all target specifications on at least 96.3% of tested design goals in schematic simulation and designed 40 operational amplifiers that passed layout checks in 68 hours; a language-model agent designed 20 analog circuits in its authors' benchmark, and they say models cannot yet design highly complex analog circuits. The designs are standard circuit types, and an engineer still chooses the topology and the specification.

Academic studies on standard circuits; they do not show use in commercial analog design.

Tool scripts and design flows

This is where AI help is most direct. NVIDIA built domain-adapted models for its own chip designers, and its paper reports that the largest outperformed GPT-4 at answering engineering questions and generating tool scripts.

A company's evaluation of its own internal models; it does not say how much of engineers' time changed.