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Chip design engineer
Designs integrated circuits: turns an architecture into hardware description code (RTL), verifies that the design does what the specification says, lays it out on silicon to meet power, performance and area, and designs the analog blocks that connect a chip to the physical world. AI now writes short pieces of hardware code, answers engineers' questions and writes tool scripts, and design-space optimisation tools have been used in more than 100 commercial tape-outs, according to the vendor. But on a benchmark written by experienced hardware engineers the best models passed no more than 34% of code-generation problems on the first try, verification is among the hardest tasks for AI agents, and an independent review found human experts beat Google's reinforcement-learning placement on most large designs it tested. The US projects computer hardware engineer employment to grow 9 percent to 2035, without mentioning AI.
Ask an AI assistant to write a block you have already built, run your testbench on it and note what fails.
This is not a probability of losing your job. It combines how much of the role's task load is exposed to automation with how far adoption has actually gone — useful for comparing occupations on one consistent basis, and for nothing else.
Written for engineers who design integrated circuits — RTL design, design verification, physical design and analog or custom design. Electrical engineers working on power systems, buildings and boards have their own page, and so do software engineers. The evidence is benchmarks of AI models on hardware code, a chip company's paper on its internal models, a published chip-layout method and an independent review of it, two academic analog-design studies, a US labour projection and a design-tool vendor's announcement; it establishes what AI can do on design tasks and where it falls short, not how chip-design jobs or pay have changed.
The evidence base holds verified records for other occupations, but not one for this one yet. Until it does, the analysis below is reasoning about task structure and known technical capability — for this job in particular it is not backed by traceable sources, and we would rather say so than cite things we have not verified. An empty section here is a gap in our coverage, not a finding about the work.
What is actually changing#
The unit of analysis is the task, not the job title. A role is not replaced — its task mix shifts.
Each tile is one task. Its size is how much of the job it is; its colour is where the task is heading. Click a tile to see what the judgement does not establish.
The absence of a record is not evidence that AI cannot help here, and the projection covers all computer hardware engineers in one country, not chip architects.
Benchmarks with models of their time; they check whether code works, not whether it meets power, performance and area, and they do not measure engineers' work.
A benchmark and a company's account of its internal models; the 60% figure comes from internal studies the paper does not publish.
The adoption figure comes from a tool vendor about its own product and the layout method is its developer's; the independent review tests a handful of designs, and none measures engineers' time.
Academic studies on standard circuits; they do not show use in commercial analog design.
A company's evaluation of its own internal models; it does not say how much of engineers' time changed.
Is this your job? Say so and this page narrows to your share of it.
A job title is a bundle of tasks bought together, and no two people hold the same bundle. Nothing is sent anywhere — it stays in this browser.
Read all 6 tasks in full — direction, reasoning and limits →
Recent changes#
United States. The statistics bureau projects employment of computer hardware engineers to grow 9 percent from 2025 to 2035, from 76,100 to 83,000, much faster than the average for all occupations, with about 4,100 openings a year. It does not mention artificial intelligence. The category covers all computer hardware engineers, including board and system hardware, not only chip designers.
A named person with standing publicly predicted something, on a date, in an attributable statement. It is recorded so that who said what, and when, stays checkable — and it never moves a task's assessment, because a prediction is not an observation. Its value arrives later: the record sits on the same page as the evidence about that occupation, so anyone reading the forecast reads the record of what happened next beside it. That is the reckoning; this site publishes no verdict on whether a forecast came true.
An academic re-evaluation of Google's reinforcement-learning macro placement using public benchmarks and a commercial place-and-route tool for post-route power, performance and area. For large macro-heavy designs, human experts beat the method in 5 of 6 comparisons; a stronger simulated-annealing baseline gave better wirelength in 7 of 9 cases, while the method gave better total negative slack than simulated annealing in 6 of 9 cases. The authors say questions about the method's scalability remain open. A handful of designs; it does not measure engineers' work.
A demo, benchmark or paper shows the task can be done. Updates what the technology can do — not what employers will do.
A benchmark of 783 problems across 13 task categories — RTL generation, verification, debugging, specification alignment and technical questions — authored by experienced hardware engineers, in both non-agentic and agentic formats. State-of-the-art models achieved no more than 34% pass@1 on code generation, and agentic tasks, especially those involving RTL reuse and verification, were particularly difficult. A test set with 2025 models; the authors' employer designs chips.
A demo, benchmark or paper shows the task can be done. Updates what the technology can do — not what employers will do.
An academic agent that designs analog circuits by generating circuit code, tested on the authors' own benchmark of analog circuit tasks. The abstract says it successfully designed 20 circuits, five more than standard GPT-4o; the paper's limitations section says LLMs currently lack the capability to design highly complex analog circuits. The authors are evaluating their own method, and the benchmark does not include extensive parameter optimisation.
A demo, benchmark or paper shows the task can be done. Updates what the technology can do — not what employers will do.
A chip company's paper on language models it adapted to its own chip-design data, evaluated on three applications: an engineering assistant chatbot, design-tool script generation, and bug summarisation and analysis. Its largest model outperformed GPT-4 on the first two and was competitive on the third. The paper says internal studies have shown that up to 60% of a typical chip designer's time is spent in debug or checklist related tasks; those studies are not published. The company evaluating its own internal models.
A demo, benchmark or paper shows the task can be done. Updates what the technology can do — not what employers will do.
A benchmark of 156 problems from the Verilog instructional website HDLBits, checked for functional correctness by simulation against a golden solution. In the corrected v2 results GPT-4 passed 43.5% of the human-written problems on the first try and 58.9% within ten tries. The authors say their evaluations are confined to boilerplate code generation for relatively small-scale designs. Models of 2023 on instructional problems; the authors' employer designs chips.
A demo, benchmark or paper shows the task can be done. Updates what the technology can do — not what employers will do.
An academic benchmark of 30 designs, built because earlier tests used designs that were relatively simple, small and proposed by their own authors. It scores syntax, functionality and design quality. GPT-4 achieved 81% correct syntax and 15 of 30 correct functionalities, where a design counts as functionally correct if any of five attempts passes the testbench. Models of 2023; it does not measure use in chip projects.
A demo, benchmark or paper shows the task can be done. Updates what the technology can do — not what employers will do.
The vendor's announcement that customers registered the first 100 commercial tape-outs with its AI design-space optimisation tool. It quotes STMicroelectronics reporting more than 3x productivity in exploring power, performance and area, SK hynix saying the tool gives its engineers more time to create differentiated features, and a Synopsys executive citing higher productivity with fewer engineering resources. The vendor describing its own product; it gives no staffing figures.
A demo, benchmark or paper shows the task can be done. Updates what the technology can do — not what employers will do.
A peer-reviewed paper by Google researchers. It says chip floorplanning has defied automation, requiring months of intense effort by physical design engineers, and that in under six hours its method generates floorplans superior or comparable to those produced by humans in power, performance and chip area; it says the method was used to design the next generation of Google's AI accelerators. An editor's note of 20 September 2023 said its performance claims had been called into question; it was removed after review. The developer's own results, disputed by independent researchers.
A demo, benchmark or paper shows the task can be done. Updates what the technology can do — not what employers will do.
An academic study. It says analog and mixed-signal modules face a long human-in-the-middle iteration loop that requires expert intuition, and presents a reinforcement-learning framework that met all target specifications on at least 96.3% of tested design goals in schematic simulation, and with the Berkeley Analog Generator designed 40 operational amplifiers that passed layout-versus-schematic checks in 68 hours, 9.6 times faster than the state of the art. Standard circuit types in a research setting.
A demo, benchmark or paper shows the task can be done. Updates what the technology can do — not what employers will do.
What this means for you#
If you are starting out, expect AI to write first drafts of small blocks and tool scripts, and build what it lacks: reading a specification closely, verifying a design, and judging power, performance and area trade-offs.
Expect optimisation tools to take more of the search in placement and sizing, and assistants to take routine code and scripts. Deciding the architecture and signing off a design stay with you.
Your options#
Four directions, each with its real constraints and one thing you can test this week. Continuing as you are is a legitimate choice — it just has to be a chosen one.
Move from writing RTL by hand to specifying and reviewing it
Models write short hardware code but fail most harder problems, so the value moves to a clear specification and a careful review.
Reviewing generated code for subtle timing or reset bugs can take as long as writing it.
Ask an AI assistant to write a block you have already built, run your testbench on it and note what fails.
Stay in verification
Verification is among the hardest tasks for AI agents, and debugging takes a large share of designers' time.
Verification roles expect deep knowledge of testbench methods and coverage.
Give an AI assistant a failing simulation log you have already debugged and check whether it finds the cause.
Move into design-automation and AI tooling for chip design
Chip companies and tool vendors are building AI into design flows, and that work depends on knowing what a correct design needs.
It requires software and machine-learning skills on top of hardware design.
Run one open hardware-code benchmark problem through an AI model and read why its answer passes or fails.
Common questions#
Not on present evidence. AI writes short hardware code and tool scripts, and optimisation tools help with placement, but the best models passed no more than 34% of code-generation problems on a benchmark written by experienced engineers, verification is among the hardest tasks for AI agents, and human experts beat Google's layout method on most large designs in an independent review. The US projects hardware engineer employment to grow 9 percent from 2025 to 2035.
We do not answer that with a number of years. Watch whether your team starts from generated RTL rather than a blank file, and how much of your time moves from writing to reviewing and verifying. Those tell you more than any date.
For short problems, often. GPT-4 passed 43.5% of 156 textbook-style problems on the first try, and newer models still passed no more than 34% of the harder problems written by experienced hardware engineers. Benchmarks check whether the code works, not whether it meets power, performance and area.
It helps. Google says its method laid out parts of its own chips and Synopsys says its tool has been used in more than 100 commercial tape-outs, but an independent review found human experts ahead on most large designs it tested, and engineers still set the constraints and close timing.
What these judgements rest on#
0 of 6 task judgements on this page are backed by a verified event and 6 are platform inference, each labelled where it appears. Behind them sit 1 technology dimensions, a reconstructed trajectory since language models reached the public, and 10 verified events.
See which technologies, how it got here, and the method →
Where it sits in the official classification: skills, knowledge, related jobs →
Other roles in the same function#
A company divides its work into functions before it divides it into jobs. These sit in Core delivery (industry-specific) alongside this one — a fact about org charts, not a judgement that they are similar or that they are changing in the same direction.
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