Samsung says it automates transistor sizing in its own analog design with reinforcement learning and genetic algorithms, roughly halving design turnaround for HBM4

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South Korea. The chipmaker's own page on a talk by the head of its device-solutions AI centre says Samsung is applying agentic AI across its design workflows with a focus on analog and logic design, has incorporated reinforcement learning and genetic algorithms to automate transistor sizing, predicts design-rule violations in advance and builds them into layout, and that design turnaround time was reduced by about 50%, enabling up to 13 Gbps per pin in HBM4. The company's own claim about its own chips; who sets the topology and specification is not stated, and the multi-agent layout workflow on the same page is a future plan.

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The company's own claim, with nothing on who sets topology and specification.

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